--
-- VHDL Architecture Fietscomputer_lib.i_serienummer.v1
--
-- Created:
--          by - Patrick.UNKNOWN (dtp7985)
--          at - 14:59:39  29-09-2011
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_UNSIGNED.all;

ENTITY fc_serienummer IS
  PORT( 
  rst           : IN     STD_LOGIC;
  Serie_reg     : OUT    STD_LOGIC_VECTOR(63 DOWNTO 0) -- 8 getallen bestaande uit 4 bit is 32 bit nodig 
);
END fc_serienummer ;

--------------------------------------------
---------------------------------------------


ARCHITECTURE v1 OF fc_serienummer IS

BEGIN

PROCESS (rst)

BEGIN
    
      Serie_reg <= "0000000000000000000000000000000000100000000100010110010100110111";

END PROCESS;  
END ARCHITECTURE v1;

